HD6417750RF240DV Datasheet, PDF (797/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 16 Serial Communication Interface with FIFO (SCIF)
The SCBRR2 setting is found from the following equation.
Asynchronous mode:
N=
Pck
× 10⁶ – 1
64 × 2^{2n – 1} × B
Where
B: Bit rate (bits/s)
N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Pck: Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR2 Setting
n
Clock
CKS1
CKS0
0
Pck
0
0
1
Pck/4
0
1
2
Pck/16
1
0
3
Pck/64
1
1
The bit rate error in asynchronous mode is found from the following equation:
Pck × 10⁶
Error (%) = _{(N + 1) × B × 64 × 22n – 1} – 1 × 100
16.2.9 FIFO Control Register (SCFCR2)
Bit: 15
14
13
12
—
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
11
10
9
8
— RSTRG2* RSTRG1* RSTRG0*
0
0
0
0
R
R/W
R/W
R/W
Bit: 7
RTRG1
Initial value: 0
R/W: R/W
6
RTRG0
0
R/W
5
TTRG1
0
R/W
4
TTRG0
0
R/W
Note: * Reserved bit in the SH7750.
3
MCE
0
R/W
2
TFRST
0
R/W
1
RFRST
0
R/W
0
LOOP
0
R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 745 of 1076