HD6417750RF240DV Datasheet, PDF (180/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
4.4 Instruction Cache (IC)
4.4.1 Configuration
The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of
256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The
SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines.
Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S.
Figure 4.7 shows the configuration of the instruction cache for the SH7750R.
Effective address
31
26 25
13 12 11 10 9
543 21 0
IIX
22
MMU
19
[12]
8
0
Address array
Tag
V
[11:5]
Longword (LW) selection
3
Data array
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
255 19 bits 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Hit signal
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013