HD6417750RF240DV Datasheet, PDF (723/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 15 Serial Communication Interface (SCI)
Note: * This bit is prepared for storing a multi-processor bit in the received data when the
receipt is carried out with a multi-processor format in asynchronous mode. This bit
does not function correctly in this LSI. However, do not use the read value from this
bit.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,
and when the operation is not transmission.
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether
transmission has been completed before changing its value.
Bit 0: MPBT
0
1
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
(Initial value)
15.2.8 Serial Port Register (SCSPTR1)
Bit: 7
6
5
4
3
2
1
0
EIO
—
—
— SPB1IO SPB1DT SPB0IO SPB0DT
Initial value: 0
0
0
0
0
—
0
—
R/W: R/W
—
—
—
R/W
R/W
R/W
R/W
SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCI) pins. Input data can be read from the
RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception
controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be
performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt.
SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0
are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined.
SCSPTR1 is not initialized in the module standby state or standby mode.
Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent
to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only
ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another
peripheral module. This bit specifies enabling or disabling of the RXI interrupt.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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