HD6417750RF240DV Datasheet, PDF (551/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
T1 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
RDY
DACKn
(SA: IO ← memory)
Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.
2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.48 Burst ROM Wait Access Timing
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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