HD6417750RF240DV Datasheet, PDF (458/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and
synchronous DRAM. This setting has priority over the BCR2 register setting.
Bit 8: SZ1
0
1
Bit 7: SZ0
0
1
0
1
Description
DRAM
SDRAM
64 bits
64 bits
Reserved (Setting prohibited) Reserved (Setting prohibited)
16 bits
Reserved (Setting prohibited)
32 bits
32 bits
Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address
multiplexing for DRAM and synchronous DRAM. The address shift value is different for the
DRAM interface and the synchronous DRAM interface.
• For DRAM Interface:
Bit 6:
AMXEXT
Bit 5:
AMX2
Bit 4:
AMX1
Bit 3:
AMX0
Description
DRAM
0*
0
0
0
8-bit column address product
(Initial value)
1
9-bit column address product
1
0
10-bit column address product
1
11-bit column address product
1
0
0
12-bit column address product
1
Reserved (Setting prohibited)
1
0
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.
Page 406 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013