HD6417750RF240DV Datasheet, PDF (394/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 12 Timer Unit (TMU)
SH7750, SH7750S, SH7750R Group
12.2.2 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters
(TCNT) are operated or stopped.
TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby
mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC
output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK)
or internal clock (Pck).
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
STR2 STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bits 7 to 3—Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Bit 2—Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or
stopped.
Bit 2: STR2
0
1
Description
TCNT2 count operation is stopped
TCNT2 performs count operation
(Initial value)
Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or
stopped.
Bit 1: STR1
0
1
Description
TCNT1 count operation is stopped
TCNT1 performs count operation
(Initial value)
Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or
stopped.
Bit 0: STR0
0
1
Description
TCNT0 count operation is stopped
TCNT0 performs count operation
(Initial value)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013