HD6417750RF240DV Datasheet, PDF (878/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 19 Interrupt Controller (INTC)
SH7750, SH7750S, SH7750R Group
NMI
IRL3–
IRL0
Input control
4
4
TMU
RTC
SCI
SCIF
WDT
REF
DMAC
H-UDI
GPIO
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
IPR
ICR
IPRA–IPRD^*1
INTPRI00^*2
Com-
parator
Interrupt
request
SR
IMASK
CPU
Bus interface
Legend:
TMU: Timer unit
RTC: Realtime clock unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
WDT: Watchdog timer
REF: Memory refresh controller section of the bus state controller
DMAC: Direct memory access controller
H-UDI: High-performance user debug interface
GPIO: I/O port
ICR: Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D^*1
INTPRI00: Interrupt priority level setting register 00^*2
SR: Status register
Notes: 1. IPRD is provided only in the SH7750S and SH7750R.
2. INTPRI00 is provided only in the SH7750R.
INTC
Figure 19.1 Block Diagram of INTC
Page 826 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013