HD6417750RF240DV Datasheet, PDF (345/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 10 Clock Oscillation Circuits
10.3 Clock Operating Modes
Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various
combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency
division ratio).
Table 10.4 shows FRQCR settings and internal clock frequencies.
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
Operating
Mode
MD2
MD1
MD0
1/2
Frequency
Divider
CPU
PLL1 PLL2 Clock
Bus
Clock
Peripheral
Module
Clock
FRQCR
Initial Value
0
0
0
0
Off
On On 6
3/2 3/2
H'0E1A
1
1
Off
On On 6
1
1
H'0E23
2
1
0
On
On On 3
1
1/2
H'0E13
3
1
Off
On On 6
2
1
H'0E13
4
1
0
0
On
On On 3
3/2 3/4
H'0E0A
5
1
Off
On On 6
3
3/2
H'0E0A
Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating
mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f_EX) and CKIO clock output (f_OP) in section 22.3.1, Clock and Control Signal
Timing.
Table 10.3 (2) Clock Operating Modes (SH7750R)
Clock
Operating
Mode
External
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Module Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2
3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
Off (×6) Off 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 293 of 1076