HD6417750RF240DV Datasheet, PDF (179/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 4 Caches
Example 3 A debugging tool generates a break to swap an instruction.
Original Instruction String After Instruction Swap Break
MOV.L #H'C000000, R0
MOV.L #H'7C000000, R0 Contains address corresponding to R0.
ADD R0, R0
TRAPA #H'01
R0 address is not a problem in original
instruction string.
MOV.L R1, @R0
MOV.L R1, @R0
Internal RAM is accessed by a store
operation because ADD is not
executed. The store is cancelled, but
2LW starting at H'7C002000 is
corrupted.
Workarounds: When RAM mode is specified in cache enhanced mode, either of the following
workarounds can be used to avoid the problem.
Workaround 1:
Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which
address bits [12:0] are identical and only bit [13] differs must not be used. For example,
the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to
H'7C002FFF may be used.
Note:
When a break is used to swap instructions by a debugging tool, etc., a memory access
address may be changed when an instruction following the instruction generating the
break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be
accessed. This will result in the problem described above. However, this phenomenon
only occurs during debugging when a break is used to swap instructions. Using a break
with no instruction swapping will not cause the problem.
Workaround 2:
Ensure that there are no instructions that generate an interrupt or exception within four
instructions after an instruction that accesses internal RAM. For example, the internal
RAM area can be used as a data table that is accessed only by load instructions, with
writes to the internal RAM area only being performed when the table is generated. It this
case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to
ensure that no exceptions due to TLB misses, etc., occur while writing to the table.
Note: The problem still may occur when a break is used to swap instructions by a debugging
tool. This phenomenon only occurs during debugging when a break is used to swap
instructions. Using a break with no instruction swapping will not cause the problem.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 127 of 1076