HD6417750RF240DV Datasheet, PDF (629/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Address Modes
Single Address Mode: In single address mode, both the transfer source and the transfer
destination are external; one is accessed by the DACK signal and the other by an address. In this
mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the
external device strobe signal (DACK) to either the transfer source or transfer destination external
device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows
an example of a transfer between external memory and an external device with DACK in which
the external device outputs data to the data bus and that data is written to external memory in the
same bus cycle.
SH7750, SH7750S,
SH7750R
DMAC
External
address
bus
External
data bus
External
memory
External device
with DACK
Legend:
: Data flow
DACK
DREQ
Figure 14.5 Data Flow in Single Address Mode
Two types of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. Only the external request signal (DREQ) is used in both these
cases.
Figure 14.6 shows the DMA transfer timing for single address mode.
The access timing depends on the type of external memory. For details, see the descriptions of the
memory interfaces in section 13, Bus State Controller (BSC).
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 577 of 1076