HD6417750RF240DV Datasheet, PDF (790/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3
to FER0 will be 0.
Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during
reception.*
Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is
cleared to 0. When a receive error occurs, the receive data is still transferred to
SCFRDR2, and reception continues.
The FER and PER bits in SCFSR2 can be used to determine whether there is a receive
error that is to be from SCFRDR2.
Bit 7: ER
0
Description
No framing error or parity error occurred during reception
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ER after reading ER = 1
(Initial value)
1
A framing error or parity error occurred during reception
[Setting conditions]
• When the SCIF checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0*
• When, in reception, the number of 1-bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by the
O/E bit in SCSMR2
Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013