HD6417750RF240DV Datasheet, PDF (660/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
3. The COUNT field is ignored if MD = 00.
4. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst
mode and cycle steal mode, a handshake protocol is used to transfer each unit of data.
5. The maximum number of transfers can be specified by setting COUNT = 0 as DTR
format initialization data. If the amount of data to be transferred is unknown, set
COUNT = 0, start DMA transfer, and transfer the DTR format (ID = 00, MD ≠ 00, SZ
= 111) when the required amount of data has been transferred. This will terminate
DMA transfer on channel 0.
In this case, the TE bit in DMA channel control register 0 is not set, but transfer cannot
be restarted.
6. When port functions are used (BCR2.PORTEN = 1) and DDT mode is selected, input
the DTR format for D[63:52] and D[31:0]. In this case, if ID[1:0] = 00, input MD[1:0]
and SZ ≠ 101, 110.
7. For DTR format transfer when ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110.
14.5.3 Transfer Request Acceptance on Each Channel
On channel 0, a DMA data transfer request can be made by means of the DTR format. No further
transfer requests are accepted between DTR format acceptance and the end of the data transfer.
On channels 1 to 3, output a transfer request from an external device by means of the DTR format
(ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal
DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer
requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored,
and so transfer requests must not be output.
When CHCR.TE = 1 when a transfer request remains in the request queue and a transfer is
completed, the request queue retains it. When another transfer request is sent at that time, the
transfer request is added to the request queue if the request queue is vacant.
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Sep 24, 2013