HD6417750RF240DV Datasheet, PDF (908/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 20 User Break Controller (UBC)
SH7750, SH7750S, SH7750R Group
20.2.3 Break ASID Register A (BASRA)
Bit: 7
BASA7
Initial value: *
R/W: R/W
Legend: *: Undefined
6
BASA6
*
R/W
5
BASA5
*
R/W
4
BASA4
*
R/W
3
BASA3
*
R/W
2
BASA2
*
R/W
1
BASA1
*
R/W
0
BASA0
*
R/W
Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID
used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual
reset.
Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used
in the channel A break conditions.
20.2.4 Break Address Mask Register A (BAMRA)
Bit: 7
6
5
4
3
2
1
0
—
—
—
— BAMA2 BASMA BAMA1 BAMA0
Initial value: 0
0
0
0
*
*
*
*
R/W: R
R
R
R
R/W R/W R/W R/W
Legend: *: Undefined
Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies
which bits are to be masked in the break ASID set in BASRA and the break address set in BARA.
BAMRA is not initialized by a power-on reset or manual reset.
Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID7
to ASID0 (BASA7–BASA0) are to be masked.
Bit 2: BASMA
0
1
Description
All BASRA bits are included in break conditions
No BASRA bits are included in break conditions
Page 856 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013