HD6417750RF240DV Datasheet, PDF (181/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Effective address
31
25
Section 4 Caches
13 12 11 10
54 2 0
IIX
22
[11:5]
[12]
Entry
selection
Address array
8
(way 0, way1)
3
0 Tag address V
Longword (LW)
selection
Data array (way 0, way 1)
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
MMU
19
255 19 bits 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit
Compare Compare
way 0 way 1
Read data
Hit signal
Figure 4.7 Configuration of Instruction Cache (SH7750R)
• Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 129 of 1076