HD6417750RF240DV Datasheet, PDF (41/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) .................................................................................................... 980
Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) .................................................................................................... 981
Figure 22.40 DRAM Burst Bus Cycle
(EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) ........................ 982
Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)............................................. 983
Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State
(EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) ................................................... 984
Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) ................................................... 985
Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) .................................................................................................... 986
Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001) .................................................................................................... 987
Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)............................................. 988
Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State
(Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ............................................ 989
Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) ............................................ 990
Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 000, TRC[2:0] = 001)..................................................................... 991
Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 001, TRC[2:0] = 001)..................................................................... 992
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) ................................. 993
Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000,
No Wait (2) TED[2:0] = 001, TEH[2:0] = 001,
One Internal Wait + One External Wait ................................................................ 994
Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000,
No Wait (2) TED[2:0] = 001, TEH[2:0] = 001,
One Internal Wait + One External Wait ................................................................ 995
Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001,
One Internal Wait, Bus Sizing).............................................................................. 996
Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait)
(2) 1st Data (One Internal Wait + One External Wait) .......................................... 997
Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait)
(2) 1st Data (One Internal Wait)
(3) 1st Data (One Internal Wait + One External Wait) .......................................... 998
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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