HD6417750RF240DV Datasheet, PDF (446/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait
states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 19: A4W2
0
1
Bit 18: A4W1
0
1
0
1
Bit 17: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States
RDY Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait
states to be inserted for area 3. External wait input is only enabled when SRAM interface or MPX
interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX
interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).
• When SRAM Interface is Set
Bit 15: A3W2
0
1
Bit 14: A3W1
0
1
0
1
Bit 13: A3W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States
RDY Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013