HD6417750RF240DV Datasheet, PDF (321/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 9 Power-Down Modes
9.3.2 Exit from Sleep Mode
Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary,
SPC and SSR should be saved to the stack before executing the SLEEP instruction.
Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep
mode is exited and interrupt exception handling is executed. The code corresponding to the
interrupt source is set in the INTEVT register.
Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the RESET pin,
or a power-on or manual reset executed when the watchdog timer overflows.
9.4 Deep Sleep Mode
9.4.1 Transition to Deep Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit
in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode.
After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to
be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory
that requires refreshing, set the self-refresh function prior to making the transition to deep sleep
mode.
In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at
the STATUS0 pin.
Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you
make a transition to deep sleep mode while DMA transfers are in progress, the results
of those transfers cannot be guaranteed.
9.4.2 Exit from Deep Sleep Mode
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 269 of 1076