HD6417750RF240DV Datasheet, PDF (233/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 5 Exceptions
5.6.4 Priority Order with Multiple Exceptions
With some instructions, such as instructions that make two accesses to memory, and the
indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple
exceptions occur. Care is required in these cases, as the exception priority order differs from the
normal order.
1. Instructions that make two accesses to memory
With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS
instructions, two data transfers are performed by a single instruction, and an exception will be
detected for each of these data transfers. In these cases, therefore, the following order is used
to determine priority.
a. Data address error in first data transfer
b. TLB miss in first data transfer
c. TLB protection violation in first data transfer
d. Initial page write exception in first data transfer
e. Data address error in second data transfer
f. TLB miss in second data transfer
g. TLB protection violation in second data transfer
h. Initial page write exception in second data transfer
2. Indivisible delayed branch instruction and delay slot instruction
As a delayed branch instruction and its associated delay slot instruction are indivisible, they
are treated as a single instruction. Consequently, the priority order for exceptions that occur in
these instructions differs from the usual priority order. The priority order shown below is for
the case where the delay slot instruction has only one data transfer.
a. A check is performed for the interrupt type and reexecution type exceptions of priority
levels 1 and 2 in the delayed branch instruction.
b. A check is performed for the interrupt type and reexecution type exceptions of priority
levels 1 and 2 in the delay slot instruction.
c. A check is performed for the completion type exception of priority level 2 in the delayed
branch instruction.
d. A check is performed for the completion type exception of priority level 2 in the delay slot
instruction.
e. A check is performed for priority level 3 in the delayed branch instruction and priority
level 3 in the delay slot instruction. (There is no priority ranking between these two.)
f. A check is performed for priority level 4 in the delayed branch instruction and priority
level 4 in the delay slot instruction. (There is no priority ranking between these two.)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 181 of 1076