HD6417750RF240DV Datasheet, PDF (935/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 21 High-performance User Debug Interface (H-UDI)
21.2 Register Descriptions
21.2.1 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial
state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is
initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to
from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed
by the CPU while writing is in progress, it may not be possible to read the correct value. In this
case, SDIR should be read twice, and then read again if the read values do not match. Operation is
undefined if a reserved command is set in this register.
SH7750, SH7750S:
Bit: 15
14
13
12
11
10
9
8
TI3
TI2
TI1
TI0
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bits 15 to 12—Test Instruction Bits (TI3−TI0)
Bit 15: TI3
0
1
Bit 14: TI2
0
1
0
1
Bit 13: TI1
—
0
1
0
1
0
1
Bit 12: TI0
—
—
0
1
—
—
—
0
1
Description
Reserved
Reserved
H-UDI reset negate
H-UDI reset assert
Reserved
H-UDI interrupt
Reserved
Reserved
Bypass mode
(Initial value)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 883 of 1076