82801FB Datasheet, PDF (95/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

System Clock Domains
4 System Clock Domains
Table 4-1 shows the ICH6 and system clock domains. Figure 4-1 and Figure 4-2 shows the
assumed connection of the various system components, including the clock generator in both
desktop and mobile systems. For complete details of the system clocking solution, refer to the
system’s clock generator component specification.
Table 4-1. Intel^® ICH6 and System Clock Domains
Clock Domain
Intel^® ICH6
SATA_CLKP,
SATA_CLKN
ICH6
DMI_CLKP,
DMI_CLKN
Frequency
100 MHz
100 MHz
ICH6
PCICLK
33 MHz
System PCI
33 MHz
ICH6
CLK48
ICH6
CLK14
48.000 MHz
14.31818 MHz
ICH6
ACZ_BIT_CLK
12.288 MHz
Source
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
AC ’97 Codec
Usage
Differential clock pair used for SATA.
Differential clock pair used for DMI.
Free-running PCI Clock to Intel^® ICH6. This clock
remains on during S0 and S1 (in desktop) state, and is
expected to be shut off during S3 or below in desktop
configurations or S1 or below in mobile configurations.
PCI Bus, LPC I/F. These only go to external PCI and
LPC devices. Will stop based on CLKRUN# (and
STP_PCI#) in mobile configurations.
Super I/O, USB controllers. Expected to be shut off
during S3 or below in desktop configurations or S1 or
below in mobile configurations.
Used for ACPI timer and Multimedia Timers. Expected
to be shut off during S3 or below in desktop
configurations or S1 or below in mobile configurations.
AC-link. Generated by AC ’97 Codec. Can be shut by
codec in D3. Expected to be shut off during S3 or below
in desktop configurations or S1 or below in mobile
configurations.
LAN_CLK
5 to 50 MHz
LAN Connect
Component
NOTE: For use only in AC ‘97 mode.
Generated by the LAN Connect component. Expected
to be shut off during S3 or below in desktop
configurations or S1 or below in mobile configurations.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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