82801FB Datasheet, PDF (330/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.7
9.1.8
9.1.9
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base Specification,
Revision 1.0a.
2:0 Reserved
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Default Value: 81h
Attribute:
Size:
RO
8 bits
Bit
Description
Multi-Function Device (MFD) — RO. The value reported here depends upon the state of the AC ‘97
function hide (FD) register (Chipset Configuration Registers:Offset 3418h), per the following table:
FD.AAD
FD.AMD
MFD
7
0
0
1
0
1
1
1
0
1
1
1
0
6:0
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the configuration space,
which is a PCI-to-PCI bridge in this case.
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18-1Ah
Default Value: 000000h
Attribute:
Size:
R/W, RO
24 bits
Bit
Description
23:16 Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the bridge.
15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
7:0 Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.
330
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet