82801FB Datasheet, PDF (667/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.32
DPUBASE—DMA Position Upper Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 74h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Position Buffer Base
31:0 Address. This register field must not be written when any DMA engine is running or the DMA
transfer may be corrupted.
18.2.33
SDCTL—Stream Descriptor Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:
Input Stream[0]: HDBAR + 80h Attribute:R/W, RO
Input Stream[1]: HDBAR + A0h
Input Stream[2]: HDBAR + C0h
Input Stream[3]: HDBAR + E0h
Output Stream[0]: HDBAR + 100h
Output Stream[1]: HDBAR + 120h
Output Stream[2]: HDBAR + 140h
Output Stream[3]: HDBAR + 160h
Default Value: 040000h
Size:24 bits
Bit
Description
23:20
Stream Number — R/W. This value reflect the Tag associated with the data being transferred on the
link.
When data controlled by this descriptor is sent out over the link, it will have its stream number
encoded on the SYNC signal.
When an input stream is detected on any of the SDI signals that match this value, the data samples
are loaded into FIFO associated with this descriptor.
Note that while a single SDI input may contain data from more than one stream number, two
different SDI inputs may not be configured with the same stream number.
19
18
17:16
15:5
4
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional streams; therefore,
this bit is hardwired to 0.
Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is enabled through
the PCI Express* registers.
Stripe Control — RO. This bit is only meaningful for input streams; therefore, this bit is hardwired to
0.
Reserved
Descriptor Error Interrupt Enable — R/W.
0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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