82801FB Datasheet, PDF (704/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.45
SMSCS—SMI/SCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: DC–DFh
Default Value: 00000000h
Attribute:
Size:
R/WC
32 bits
Bit
Description
31
Power Management SCI Status (PMCS) — R/WC. This bit is set if the Hot-Plug controller needs to
generate an interrupt, and this interrupt has been routed to generate an SCI.
30
Hot Plug SCI Status (HPCS) — R/WC. This bit is set if the Hot-Plug controller needs to generate an
interrupt, and has this interrupt been routed to generate an SCI.
29:4 Reserved
Hot Plug Command Completed SMI Status (HPCCM) — R/WC. This bit is set when SLSTS.CC
3 (D28:F0/F1/F2/F3:5A, bit 4) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
Hot Plug Attention Button SMI Status (HPABM) — R/WC. This bit is set when SLSTS.ABP
2 (D28:F0/F1/F2/F3:5A, bit 0) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
Hot Plug Presence Detect SMI Status (HPPDM) — R/WC. This bit is set when SLSTS.PDC
1 (D28:F0/F1/F2/F3:5A, bit 3) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
0
Power Management SMI Status (PMMS) — R/WC. This bit is set when RSTS.PS (D28:F0/F1/F2/
F3:60, bit 16) transitions from 0 to ’, and MPC.PMME (D28:F0/F1/F2/F3:D8, bit 1) is set.
19.1.46 VCH—Virtual Channel Capability Header Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 100–103h
Default Value: 18010002h
Attribute:
Size:
RO
32 bits
Bit
Description
31:20
19:16
15:0
Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates this is version 1 of the capability structure by the
PCI SIG.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability item.
19.1.47
VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 108–10Bh
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
23:0
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present for VC
arbitration since it is fixed.
Reserved.
704
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet