82801FB Datasheet, PDF (703/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.44
MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: D8–DBh
Default Value: 00110000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31
30
29:21
20:18
17:15
14:8
Power Management SCI Enable (PMCE) — R/W.
0 = SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is detected.
Hot Plug SCI Enable (HPCE) — R/W.
0 = SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Reserved
Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit Latency for unique-
clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3:Offset 50h:bit 6). It defaults to 512 ns to less
than 1 µs, but may be overridden by BIOS.
Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit Latency for
common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3:Offset 50h:bit 6). It defaults to 128
ns to less than 256 ns, but may be overridden by BIOS.
Reserved
Port I/OxApic Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
7
Port #
Address
1
FEC1_0000h – FEC1_7FFFh
2
FEC1_8000h – FEC1_FFFFh
3
FEC2_0000h – FEC2_7FFFh
4
FEC2_8000h – FEC2_FFFFh
6:2 Reserved
Hot Plug SMI Enable (HPME) — R/W.
1 _{0 = SMI generation based on a Hot-Plug event is disabled.}
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
Power Management SMI Enable (PMME) — R/W.
0 _{0 = SMI generation based on a power management event is disabled.}
1 = Enables the root port to generate SMI whenever a power management event is detected.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
703