82801FB Datasheet, PDF (66/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-12. Power Management Interface Signals (Sheet 2 of 2)
Name
Type
Description
LAN_RST#
LAN Reset: When asserted, the internal LAN controller will be put into reset. This
signal must be asserted for at least 10 ms after the resume well power (VccSus3_3
and VccSus1_5 in desktop and VccLAN3_3 and VccLAN1_5 in mobile) is valid.
I
When de-asserted, this signal is an indication that the resume (LAN for mobile) well
power is stable.
NOTE: LAN_RST# must de-assert at some point to complete ICH6 power up
sequencing.
WAKE#
I
PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by
components requesting wakeup.
MCH_SYNC#
MCH SYNC: This input is internally ANDed with the PWROK input.
I Desktop: Connected to the ICH_SYNC# output of (G)MCH.
Mobile: Refer to the Platform Design Guide.
SUS_STAT# /
LPCPD#
Suspend Status: This signal is asserted by the ICH6 to indicate that the system will
be entering a low power state soon. This can be monitored by devices with memory
O that need to switch from normal refresh to suspend refresh mode. It can also be
used by other peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F.
SUSCLK
O
Suspend Clock: This clock is an output of the RTC generator circuit to be used by
other chips for refresh clock.
VRMPWRGD
VRM Power Good: This should be connected to be the processor’s VRM Power
I Good signifying the VRM is stable. This signal is internally ANDed with the PWROK
input.
Bus Master Busy: To support the C3 state. Indication that a bus master device is
busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes
BMBUSY#
active in a C3 state, it is treated as a break event.
(Mobile Only) /
GPI[6]
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NOTES:
(Desktop Only)
1. This signal is internally synchronized using the PCICLK and a two-stage
synchronizer. It does not need to meet any particular setup or hold time.
2. In desktop configurations, this signal is a GPI.
STP_PCI#
(Mobile Only) /
GPO[18]
(Desktop Only)
O
Stop PCI Clock: This signal is an output to the external clock generator for it to turn
off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is
not needed, this signal can be configured as a GPO.
STP_CPU#
(Mobile Only) /
GPO[20]
(Desktop Only)
O
Stop Processor Clock: This signal is an output to the external clock generator for it
to turn off the processor clock. It is used to support the C3 state. If this functionality
is not needed, this signal can be configured as a GPO.
BATLOW#
(Mobile Only) /
TP[0]
(Desktop Only)
I
Battery Low: This signal is an input from battery to indicate that there is insufficient
power to boot the system. Assertion will prevent wake from S3–S5 state. This signal
can also be enabled to cause an SMI# when asserted.
DPRSLPVR
Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM
(Mobile Only) /
TP[1]
O
during the C4 state. When the signal is high, the voltage regulator outputs the lower
“Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher
(Desktop Only)
“Normal” voltage.
DPRSTP#
(Mobile Only) /
TP[4]
O Deeper Sleep: This is a copy of the DPRSLPVR and it is active low.
(Desktop Only)
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet