82801FB Datasheet, PDF (337/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.21
PDPR—PCI Decode Policy Register
(PCI-PCI—D30:F0)
Offset Address: 42h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved
Subtractive Decode Policy (SDP) — R/W.
0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other
device on the backbone (primary interface) to the PCI bus (secondary interface).
0 _{1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the corresponding}
Space Enable bit is set in the Command register.
NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
337