82801FB Datasheet, PDF (785/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Testability
Table 24-6. XOR Chain #4-2 (REQ[4:1]# = 0011)
Pin Name
LAN_RXD[2]
EE_SHCLK
LAN_TXD[0]
LAN_TXD[2]
Ball #
C13
B12
C12
E13
Notes
Top of XOR Chain
2nd signal in XOR
EE_CS
D12
LAN_RSTSYNC B11
EE_DIN
F13
LAN_RXD[0]
E12
LAN_TXD[1]
C11
EE_DOUT
D11
LAN_RXD[1]
E11
LAN_CLK
F12
CLK14
E10
SPKR
F8
GPI[12]
M2
GPIO[25]
P5
PME#
P6
PCIRST#
R2
GPIO[27]
R3
GPI[13]
R6
GPIO[28]
T3
SLP_S5#
T6
SLP_S4#
T5
SLP_S3#
T4
WAKE#
U5
2
Pin Name
SMLINK[1]
SYS_RESET#
GPIO[24]
SUSCLK
SUS_STAT#/
LPCPD#
SMLINK[0]
SMBDATA
SMBCLK
SMBALERT#/
GPI[11]
LINKALERT#
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
SATA[3]RXN/
RESERVED
SATA[3]RXP/
RESERVED
SATA[3]TXN/
RESERVED
SATA[3]TXP/
RESERVED
SATA[3]GP/
GPI[31]
SATALED#
SATA[2]GP/
GPI[30]
SERIRQ
FERR#
SMI#
IGNNE#
PLTRST#
Ball #
U6
U2
V3
V6
Notes
26th signal in XOR
W3
W4
W5
Y4
W6
Y5
AD7
AC7
AF6
AG6
AC9
AD9
AF8
AG8
AG18
AC19
AF18
AB20
AF24
AG27
AG26
R5
XOR Chain #4-2
OUTPUT
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
785