82801FB Datasheet, PDF (162/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.14.7.4
PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE#
pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS
register.
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages.
When a PME message is received, ICH6 will set the PCI_EXP_STS bit.
5.14.7.5
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different transitions
could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should boot once
power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state
(unless previously in S4). There are only three possible events that will wake the system after a
power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3
state), the PWRBTN_STS bit is reset. When the ICH6 exits G3 after power returns
(RSMRST# goes high), the PWRBTN# signal is already high (because V_CC-standby goes high
before RSMRST# goes high) and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event,
it is important to keep this signal powered during the power loss event. If this signal goes low
(active), when power returns the RI_STS bit is set and the system interprets that as a wake
event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like
PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The ICH6 monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes
low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.
PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Table 5-32. Transitions Due to Power Failure
State at Power Failure
S0, S1, S3
S4
S5
AFTERG3_EN bit
1
0
1
0
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
162
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet