82801FB Datasheet, PDF (481/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
Bits
Description
BIST FIS Successful (BFS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
11 ^{1 = This bit is set any time a BIST FIS transmitted by ICH6 receives an R_OK completion status}
from the device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
10 ^{1 = This bit is set any time a BIST FIS transmitted by ICH6 receives an R_ERR completion status}
from the device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the
9
(Desktop
Only)
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
9
(Mobile Reserved.
Only)
Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 0, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 0 is
8
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST FIS Pattern
Definition in any BIST FIS transmitted by the ICH6. This field is not port specific — its contents will
be used for any BIST FIS initiated on port 0, port 1, port 2 or port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
7:2 ^{Bit 6: A – Align Bypass mode}
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
1:0 Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
481