82801FB Datasheet, PDF (277/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.56
FD—Function Disable Register
Offset Address: 3418–341Bh
Default Value: See bit description
Attribute:
Size:
R/W, RO
32-bit
The UHCI functions must be disabled from highest function number to lowest. For example, if
only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set). When disabling
UHCIs, the EHCI Structural Parameters Registers must be updated with coherent information in
“Number of Companion Controllers” and “N_Ports” fields.
When disabling a function, only the configuration space is disabled. Software must ensure that all
functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA
engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled function can
only be re-enabled by a platform reset.
Bit
31:20
19
18
17
16
15
14
13:12
11
10
Description
Reserved
PCI Express 4 Disable (PE4D) — R/W. Default is 0. When disabled, the link for this port is put
into the “link down” state.
0 = PCI Express* port #4 is enabled.
1 = PCI Express port #4 is disabled.
PCI Express 3 Disable (PE3D) — R/W. Default is 0. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #3 is enabled.
1 = PCI Express port #3 is disabled.
PCI Express 2 Disable (PE2D) — R/W. Default is 0. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #2 is enabled.
1 = PCI Express port #2 is disabled.
PCI Express 1 Disable (PE1D) — R/W. Default is 0. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #1 is enabled.
1 = PCI Express port #1 is disabled.
EHCI Disable (EHCID) — R/W. Default is 0.
0 = The EHCI is enabled.
1 = The EHCI is disabled.
LPC Bridge Disable (LBD) — R/W. Default is 0.
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional
spaces will no longer be decoded by the LPC bridge:
• Memory cycles below 16 MB (1000000h)
• I/O cycles below 64 kB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but
the aliases at the top of 1 MB (the E and F segment) no longer will be decoded.
Reserved
UHCI #4 Disable (U4D) — R/W. Default is 0.
0 = The 4th UHCI (ports 6 and 7) is enabled.
1 = The 4th UHCI (ports 6 and 7) is disabled.
UHCI #3 Disable (U3D) — R/W. Default is 0.
0 = The 3rd UHCI (ports 4 and 5) is enabled.
1 = The 3rd UHCI (ports 4 and 5) is disabled.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
277