82801FB Datasheet, PDF (340/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.24
9.1.25
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0)
Offset Address: 4C–4Fh
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:7 Reserved
PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR# Assertion status bit
6
(in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary
side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register).
SERR# is a source of NMI.
Secondary Discard Timer Testmode (SDTT) — R/W.
5 _{0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9)}
1 = The secondary discard timer will expire after 128 PCI clocks.
4:3 Reserved
2 Reserved
1 Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will report
0 SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and
CMD.SEE (D30:F0:04 bit 8) is set.
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address: 50–51h
Default Value: 000Dh
Attribute:
Size:
RO
16 bits
Bit
Description
15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
7:0
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor
capability.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet