82801FB Datasheet, PDF (101/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.2
PCI Express* Root Ports (D28:F0,F1,F2,F3)
PCI Express is the next generation high performance general input/output architecture. PCI
Express is a high speed, low voltage, serial pathway for two devices to communicate
simultaneously by implementing dual unidirectional paths between two devices. PCI Express has
been defined to be 100-percent compatible with conventional PCI compliant operating systems and
their corresponding bus enumeration and configuration software. All PCI Express hardware
elements have been defined with a PCI-compatible configuration space representation.
PCI Express replaces the device-based arbitration process of conventional PCI with flow-control -
based link arbitration that allows data to pass up and down the link based upon traffic class priority.
High priority is given to traffic classes that require guaranteed bandwidth such as isochronous
transactions while room is simultaneously made for lower priority transactions to avoid
bottlenecks.
The ICH6 provides 4 (x1) PCI Express ports with each port supporting up to 5 Gb/s concurrent
bandwidth (2.5 Gb/s in each direction). These all reside in device 28, and take function 0 – 3. Port
1 is function 0, port 2 is function 1, port 3 is function 2, and port 4 is function 3.
5.2.1 Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management events, when
enabled. These interrupts can either be pin based, or can be MSIs, when enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to the ICH6 interrupt
controllers. The pin that is driven is based upon the setting of the chipset configuration registers.
Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and
D28IR (Base address + 3146h) registers.
The following table summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Table 5-2. MSI vs. PCI IRQ Actions
Interrupt Register
Wire-Mode Action MSI Action
All bits 0
One or more bits set to 1
Wire inactive
Wire active
One or more bits set to 1, new bit gets set to 1
Wire active
One or more bits set to 1, software clears some (but not all) bits
Wire active
One or more bits set to 1, software clears all bits
Wire inactive
Software clears one or more bits, and one or more bits are set on the
same clock
Wire active
No action
Send
message
Send
message
Send
message
No action
Send
message
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
101