82801FB Datasheet, PDF (151/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.14.2 Intel^® ICH6 and System Power States
Table 5-24 shows the power states defined for ICH6-based platforms. The state names generally
match the corresponding ACPI states.
Table 5-24. General Power States for Systems Using Intel^® ICH6
State/
Substates
Legacy Name / Description
G0/S0/C0
G0/S0/C1
G0/S0/C2
(Mobile Only)
G0/S0/C3
(Mobile Only)
G0/S0/C4
(Mobile Only)
G1/S1
G1/S3
G1/S4
G2/S5
G3
Full On: Processor operating. Individual devices may be shut down to save power. The
different processor operating levels are defined by Cx states, as shown in Table 5-25. Within
the C0 state, the Intel^® ICH6 can throttle the processor using the STPCLK# signal to reduce
power consumption. The throttling can be initiated by software or by the operating system or
BIOS.
Auto-Halt: Processor has executed an AutoHalt instruction and is not executing code. The
processor snoops the bus and maintains cache coherency.
Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a
Stop-Grant cycle, halts its instruction stream, and remains in that state until the STPCLK#
signal goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains
cache coherency.
Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a
Stop-Grant cycle, halts its instruction stream. ICH6 then asserts DPSLP# followed by
STP_CPU#, which forces the clock generator to stop the processor clock. This is also used
for Intel SpeedStep^® technology support. Accesses to memory (by graphics, PCI, or internal
units) is not permitted while in a C3 state.
Stop-Clock with Lower Processor Voltage: This closely resembles the G0/S0/C3 state.
However, after the ICH6 has asserted STP_CPU#, it then lowers the voltage to the
processor. This reduces the leakage on the processor. Prior to exiting the C4 state, the ICH6
increases the voltage to the processor.
Stop-Grant: Similar to G0/S0/C2 state. ICH6 also has the option to assert the CPUSLP#
signal to further reduce processor power consumption.
NOTE: The behavior for this state is slightly different when supporting iA64 processors.
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is
shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop
except RTC clock.
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is
then shut off to the system except for the logic required to resume.
Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic
required to restart. A full boot is required when waking.
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for
the RTC. No “Wake” events are possible, because the system does not have any power. This
state occurs if the user removes the batteries, turns off a mechanical switch, or if the system
power supply is at a level that is insufficient to power the “waking” logic. When system power
returns, transition will depends on the state just prior to the entry to G3 and the AFTERG3 bit
in the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-32 for more details.
Table 5-25 shows the transitions rules among the various states. Note that transitions among the
various states may appear to temporarily transition through intermediate states. For example, in
going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate
transitions and states are not listed in the table.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
151