82801FB Datasheet, PDF (564/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.1.2
15.1.3
DID—Device Identification Register (SMBus—D31:F3)
Address:
Default Value:
02–03h
266Ah
Attribute:
Size:
RO
16 bits
Bit
15:0 Device ID — RO.
Description
PCICMD—PCI Command Register (SMBus—D31:F3)
Address:
Default Value:
04–05h
0000h
Attributes:RO, R/W
Size:16 bits
Bit
Description
15:11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Enables SERR# generation.
1 = Disables SERR# generation.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
0 = Disable
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Hardwired to 0.
Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet