82801FB Datasheet, PDF (576/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.12
.
AUX_CTL—Auxiliary Control Register (SMBus—D31:F3)
Register Offset:
Default Value:
Lockable:
SMBASE + 0Dh
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7:2 Reserved
Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 _{1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to}
a single register. This enables the block commands to transfer or receive up to 32-bytes before
the ICH6 generates an interrupt.
Automatically Append CRC (AAC) — R/W.
0 = ICH6 will Not automatically append the CRC.
0 _{1 = The ICH6 will automatically append the CRC. This bit must not be changed during SMBus}
transactions or undetermined behavior will result. It should be programmed only once during the
lifetime of the function.
15.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBus—D31:F3)
Register Offset: SMBASE + 0Eh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
Bit
Description
7:3 Reserved
SMLINK_CLK_CTL — R/W.
0 = ICH6 will drive the SMLINK0 pin low, independent of what the other SMLINK logic would
2
otherwise indicate for the SMLINK0 pin.
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state of the pin.
(Default)
SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK1 pin. This allows software to read the current
1 ^{state of the pin.}
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK0 pin. This allows software to read the current
0 ^{state of the pin.}
0 = Low
1 = High
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet