82801FB Datasheet, PDF (486/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.3 AHCI Registers (D31:F2)
Note: These registers are AHCI-specific and available only on ICH6R and ICH6-M when properly
configured. The Serial ATA Status, Control, and Error registers are special exceptions and may be
accessed on all ICH6 components if properly configured; see Section 12.1.31 for details.
The memory mapped registers within the SATA controller exist in non-cacheable memory space.
Additionally, locked accesses are not supported. If software attempts to perform locked
transactions to the registers, indeterminate results may occur. Register accesses shall have a
maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary.
The registers are broken into two sections – generic host control and port control. The port control
registers are the same for all ports, and there are as many registers banks as there are ports.
Table 12-3. AHCI Register Address Map
ABAR +
Offset
Mnemonic
Register
00h–1Fh
GHC Generic Host Control
20h–FFh
—
Reserved
100h–17Fh
180h–1FFh
200h–27Fh
P0PCR
P1PCR
P2PCR
Port 0 port control registers
Port 1 port control registers (Desktop Only)
Registers are not available and software must not read or write registers. (Mobile
Only)
Port 2 port control registers
280h–2FFh
300h–3FFh
P3PCR
—
Port 3 port control registers (Desktop Only)
Registers are not available and software must not read or write registers. (Mobile
Only)
Reserved
12.3.1 AHCI Generic Host Control Registers (D31:F2)
Table 12-4. Generic Host Controller Register Address Map
ABAR +
Offset
00h–03h
04h–07h
08h–0Bh
0Ch–0Fh
10h–13h
Mnemonic
CAP
GHC
IS
PI
VS
Register
Host Capabilities
Global ICH6 Control
Interrupt Status
Ports Implemented
AHCI Version
Default
C6027F03h
00000000h
00000000h
00000000h
00010000h
Type
R/WO, RO
R/W
R/WC, RO
R/WO, RO
RO
486
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet