82801FB Datasheet, PDF (442/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.8
BCC—Base Class Code Register (IDE—D31:F1)
Address Offset: 0Bh
Default Value: 01h
Attribute: RO
Size:
8 bits
Bit
Base Class Code (BCC) — RO.
7:0
01 = Mass storage device
Description
11.1.9
CLS—Cache Line Size Register (IDE—D31:F1)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Cache Line Size (CLS) — RO.
7:0
00h = Hardwired. The IDE controller is implemented internally so this register has no meaning.
11.1.10
PMLT—Primary Master Latency Timer Register
(IDE—D31:F1)
Address Offset: 0Dh
Default Value: 00h
Attribute: RO
Size:
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO.
7:0 _{00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as a PCI device,}
so it does not need a Master Latency Timer.
11.1.11
.
PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset: 10h–13h
Default Value: 00000001h
Attribute: R/W, RO
Size:
32 bits
Bit
Description
31:16 Reserved
15:3 Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet