82801FB Datasheet, PDF (361/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.27
RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bit
Bit
Description
31:14
13:1
0
Base Address (BA) — R/W. This field provides the base address for the root complex register block
decode range. This address is aligned on a 16-KB boundary.
Reserved
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed as the Root
Complex Register Block.
10.2 DMA I/O Registers (LPC I/F—D31:F0)
Table 10-2. DMA Registers (Sheet 1 of 2)
Port
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
80h
81h
82h
83h
84h–86h
87h
88h
Alias
10h
11h
12h
13h
14h
15h
16h
17h
18h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
90h
91h
—
93h
94h–96h
97h
98h
Register Name
Channel 0 DMA Base & Current Address
Channel 0 DMA Base & Current Count
Channel 1 DMA Base & Current Address
Channel 1 DMA Base & Current Count
Channel 2 DMA Base & Current Address
Channel 2 DMA Base & Current Count
Channel 3 DMA Base & Current Address
Channel 3 DMA Base & Current Count
Channel 0–3 DMA Command
Channel 0–3 DMA Status
Channel 0–3 DMA Write Single Mask
Channel 0–3 DMA Channel Mode
Channel 0–3 DMA Clear Byte Pointer
Channel 0–3 DMA Master Clear
Channel 0–3 DMA Clear Mask
Channel 0–3 DMA Write All Mask
Reserved Page
Channel 2 DMA Memory Low Page
Channel 3 DMA Memory Low Page
Channel 1 DMA Memory Low Page
Reserved Pages
Channel 0 DMA Memory Low Page
Reserved Page
Default
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
000001XXb
000000XXb
Undefined
Undefined
Undefined
0Fh
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
RO
WO
WO
WO
WO
WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
361