82801FB Datasheet, PDF (104/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.2.4.2
5.2.4.3
When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and
sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an
interrupt.
Message Generation
When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3:Offset 58h:bits 7:6) or
SLCTL.PIC (D28:F0/F1/F2/F3:Offset 58h:bits 9:8), the root port will send a message down the
link to change the state of LEDs on the module.
Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When
receiving one of these writes, the root port performs the following:
• Changes the state in the register
• Generates a completion into the upstream queue
• Formulates a message for the downstream port if the field is written to regardless of if the field
changed
• Generates the message on the downstream port
• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/F2/
F3:Offset 58h:bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE
(D28:F0/F1/F2/F3:Offset 58h:bit 5) are set, the root port generates an interrupt.
The command completed register (SLSTS.CC) applies only to commands issued by software to
control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller
(SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up
writing to the indicators and power controller fields. Hence, any write to the Slot Control Register
is considered a command and if enabled, will result in a command complete interrupt. The only
exception to this rule is a write to disable the command complete interrupt which will not result in
a command complete interrupt.
A single write to the Slot Control register is considered to be a single command, and hence receives
a single command complete, even if the write affects more than one field in the Slot Control
Register.
Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user. This attention
button press will result in a the PCI Express message “Attention_Button_Pressed” from the device.
Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3:Offset
5Ah:bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/F3:Offset
58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated
on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet