82801FB Datasheet, PDF (200/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-44. USB Legacy Keyboard State Transitions
Current State
IDLE
IDLE
IDLE
IDLE
IDLE
GateState1
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
GateState2
GateState2
GateState2
Action
64h / Write
64h / Write
64h / Read
60h / Write
60h / Read
60h / Write
64h / Write
64h / Write
60h / Read
64h / Read
64 / Write
64h / Write
64h / Read
60h / Write
60h / Read
Data Value
D1h
Not D1h
N/A
Don't Care
N/A
XXh
D1h
Not D1h
N/A
N/A
FFh
Not FFh
N/A
XXh
N/A
Next State
Comment
GateState1
IDLE
IDLE
IDLE
IDLE
GateState2
GateState1
ILDE
IDLE
GateState1
IDLE
IDLE
Standard D1 command. Cycle passed through to
8042. SMI# doesn't go active. PSTATE (offset C0,
bit 6) goes to 1.
Bit 3 in Configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Bit 2 in Configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Bit 1 in Configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Bit 0 in Configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Cycle passed through to 8042, even if trap enabled
in Bit 1 in Configuration Register. No SMI#
generated. PSTATE remains 1. If data value is not
DFh or DDh then the 8042 may chose to ignore it.
Cycle passed through to 8042, even if trap enabled
via Bit 3 in Configuration Register. No SMI#
generated. PSTATE remains 1. Stay in GateState1
because this is part of the double-trigger
sequence.
Bit 3 in Configuration space determines if cycle
passed through to 8042 and if SMI# generated.
PSTATE goes to 0. If Bit 7 in Configuration
Register is set, then SMI# should be generated.
This is an invalid sequence. Bit 0 in Configuration
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0. If
Bit 7 in Configuration Register is set, then SMI#
should be generated.
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Configuration Register. PSTATE
remains 1.
Standard end of sequence. Cycle passed through
to 8042. PSTATE goes to 0. Bit 7 in Configuration
Space determines if SMI# should be generated.
Improper end of sequence. Bit 3 in Configuration
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0. If
Bit 7 in Configuration Register is set, then SMI#
should be generated.
GateState2
IDLE
IDLE
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Configuration Register. PSTATE
remains 1.
Improper end of sequence. Bit 1 in Configuration
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0. If
Bit 7 in Configuration Register is set, then SMI#
should be generated.
Improper end of sequence. Bit 0 in Configuration
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0. If
Bit 7 in Configuration Register is set, then SMI#
should be generated.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet