82801FB Datasheet, PDF (432/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.10.4
GP_LVL—GPIO Level for Input or Output Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +0Ch
FF3F0000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit descriptions
Bit
31:29
28:27
26
25:24
23:16
15:0
Description
GP_LVL[31:29] — R/W. These bits correspond to input-only GPI in the core well. The
corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes to these
bits will have no effect.
Since these bits correspond to GPI that are in the core well, these bits will be reset by PLTRST#.
0 = Low
1 = High
GP_LVL[28:27] — R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in
the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to
drive a high or low value on the output pin. 1 = high, 0 = low.
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the
input signal (1 = high, 0 = low.). Writes will have no effect.
Since these bits correspond to GPIO that are in the Resume well, these bits will be reset by
RSMRST# and also by a write to the CF9h register.
0 = Low
1 = High
GP_LVL[26] — R/W. This bit corresponds to an input-only GPI in the core well. The
corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes to this bit
will have no effect.
Since this bit correspond to a GPI that is in the core well, this bit will be reset by PLTRST#.
0 = Low
1 = High
GP_LVL[25:24] — R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in
the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to
drive a high or low value on the output pin. 1 = high, 0 = low.
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the
input signal (1 = high, 0 = low.). Writes will have no effect.
Since these bits correspond to GPIO that are in the Resume well, these bits will be reset by
RSMRST# and also by a write to the CF9h register.
0 = Low
1 = High
GP_LVL[23:16] — R/W. These bits can be updated by software to drive a high or low value on the
output pin. These bits correspond to GPIO that are in the core well, and will be reset to their
default values by PLTRST#.
0 = Low
1 = High
Reserved. (These bits are not needed, as the level of general purpose inputs can be read through
the registers in the ACPI I/O space).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet