82801FB Datasheet, PDF (88/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Pin States
Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 4 of 4)
Signal Name
Power
Plane
During
Immediately
PLTRST#⁶ / after PLTRST#⁶ /
RSMRST#⁷
RSMRST#⁷
C3/C4
S1
S3_COLD13 S4/S5
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
ACZ_BIT_CLK
GPO[19]
GPO[21]
GPO[23]
GPIO[24]
GPIO[25]
GPIO[28:27]
VccSus3_3
Vcc3_3
Vcc3_3
Vcc3_3
Intel High Definition Audio Interface
Low
Low¹¹
High
High-Z with
Internal Pull-
down
Running
Running
High-Z with
Internal Pull-
down
Running
Running
High-Z with
Internal Pull-
down
Low¹¹
Running
Unmultiplexed GPIO Signals
Vcc3_3
Vcc3_3
Vcc3_3
VccSus3_3
VccSus3_3
High
High
Low
High
High
High
High
Low
High
High9
Defined
Defined
Defined
Defined
Defined
VccSus3_3
High
High
Defined
TBD
Low
Low
Low
Defined
Defined
Defined
Defined
Defined
Defined
Low
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
Off
Off
Defined
Defined
Defined
GPIO[34:33]
Vcc3_3
High
High
Defined Defined
Off
Off
NOTES:
1. ICH6 drives these signals Low before PWROK rising and High after the processor reset.
2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH6 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH6’s VRMPWRGD and PWROK
signals, and thus will be driven low by ICH6 when either VRMPWRGD or PWROK are inactive. During boot,
or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z.
4. LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3-S5 states depending upon whether
or not the LAN power planes are active.
5. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is
disabled.
6. The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#.
7. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#.
8. ICH6 drives these signals Low before PWROK rising and Low after the processor reset.
9. GPIO[25] transitions from pulled high internally to actively driven following the de-assertion of the RSMRST#
pin.
10.SLP_S5# signals will be high in the S4 state.
11.Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time
ACZ_RST# will be High and ACZ_BIT_CLK will be Running.
12.PETp/n[4:1] high until port is enabled by software.
13.In S3_HOT, signal states are platform implementation specific, as some external components and interfaces
may be powered when the ICH6 is in the S3_HOT state.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet