82801FB Datasheet, PDF (349/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
40–43h
00000001h
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO
32 bit
ACPI, Legacy
Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These registers
can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
Bit
31:16
15:7
6:1
0
Description
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic.
This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
10.1.13
ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W
8 bit
ACPI, Legacy
Core
Bit
Description
ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
7 _{1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power}
management function is enabled. Note that the APM power management ranges (B2/B3h) are
always enabled and are not affected by this bit.
6:3 Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W. This field specifies on which IRQ the SCI will internally
appear. If not using the APIC, the SCI must be routed to IRQ9–11, and that interrupt is not sharable
with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can
also be mapped to IRQ20–23, and can be shared with other interrupts.
Bits
SCI Map
000b
IRQ9
001b
IRQ10
2:0
010b
IRQ11
011b
Reserved
100b
IRQ20 (Only available if APIC enabled)
101b
IRQ21 (Only available if APIC enabled)
110b
IRQ22 (Only available if APIC enabled)
111b
IRQ23 (Only available if APIC enabled)
NOTE: When the TCO interrupt is mapped to APIC interrupts 9, 10 or 11, the signal is in fact active
high. When the TCO interrupt is mapped to IRQ 20, 21, 22, or 23, the signal is active low
and can be shared with PCI interrupts that may be mapped to those same signals (IRQs).
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
349