82801FB Datasheet, PDF (541/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
Bit
Description
SMI on OS Ownership Enable — R/W.
13
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7:6Ch, bit 29) is 1, the
host controller will issue an SMI.
12:6 Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
5
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7:6Ch, bit 21) is a 1, the
host controller will issue an SMI immediately.
SMI on Host System Error Enable — R/W.
4 ^{0 = Disable.}
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7:6Ch, bit 20) is a 1, the
host controller will issue an SMI.
SMI on Frame List Rollover Enable — R/W.
3 ^{0 = Disable.}
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7:6Ch, bit 19) is a 1,
the host controller will issue an SMI.
SMI on Port Change Enable — R/W.
2
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7:6Ch, bit 18) is a 1,
the host controller will issue an SMI.
SMI on USB Error Enable — R/W.
1 ^{0 = Disable.}
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7:6Ch, bit 17) is a 1, the host
controller will issue an SMI immediately.
SMI on USB Complete Enable — R/W.
0 ^{0 = Disable.}
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7:6Ch, bit 16) is a 1, the
host controller will issue an SMI immediately.
14.1.28
SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7)
Address Offset: 70–73h
Attribute:
Default Value:
00000000h
Size:
Power Well:
Suspend
NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
R/W, R/WC
32 bits
Bit
Description
31:30 Reserved — RO. Hardwired to 00h
29:22
SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 29:22 correspond to the Port Owner bits for ports 1 (22) through 8 (29). These bits are set
to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0.
SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
21 ^{0 = Power State bits Not modified.}
1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR)
register (D29:F7:54h).
SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
20 _{0 = No Async Schedule Enable bit change}
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
541