82801FB Datasheet, PDF (346/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
06–07h
0200h
No
Attribute:
Size:
Power Well:
RO, R/WC
16-bit
Core
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity error on the
internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0
15
0 = Parity Error Not detected.
1 = Parity Error detected.
14
Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system error to the
internal SERR# logic.
Master Abort Status (RMA) — R/WC.
13
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the backbone.
Received Target Abort (RTA) — R/WC.
12
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Signaled Target Abort (STA) — R/WC.
11
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
8
• LPC bridge receives a completion packet from the backbone from a previous request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
7
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal backbone.
6
Reserved.
5
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal backbone.
4
Capabilities List (CLIST) — RO. No capability list exist on the LPC bridge.
3
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
2:0 Reserved.
346
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet