82801FB Datasheet, PDF (233/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.22.4
AC ’97 Cold Reset
A cold reset is achieved by asserting ACZ_RST# for 1 µs. By driving ACZ_RST# low,
ACZ_BIT_CLK, and ACZ_SDOUT will be activated and all codec registers will be initialized to
their default power on reset values. ACZ_RST# is an asynchronous AC ’97 input to the codec.
5.22.5 AC ’97 Warm Reset
A warm reset re-activates the AC-link without altering the current codec register values. A warm
reset is signaled by driving ACZ_SYNC high for a minimum of 1 µs in the absence of
ACZ_BIT_CLK.
Within normal frames, ACZ_SYNC is a synchronous AC ’97 input to the codec. However, in the
absence of ACZ_BIT_CLK, ACZ_SYNC is treated as an asynchronous input to the codec used in
the generation of a warm reset.
The codec must not respond with the activation of ACZ_BIT_CLK until ACZ_SYNC has been
sampled low again by the codec. This prevents the false detection of a new frame.
Note: On receipt of wake up signaling from the codec, the digital controller issues an interrupt if enabled.
Software then has to issue a warm or cold reset to the codec by setting the appropriate bit in the
Global Control Register.
5.22.6
Hardware Assist to Determine ACZ_SDIN Used Per Codec
Software first performs a read to one of the audio codecs. The read request goes out on
ACZ_SDOUT. Since the ICH6 allows one read to be performed at a time on the link, eventually
the read data will come back in on one of the ACZ_SDIN[2:0] lines.
The codec does this by indicating that status data is valid in its TAG, then echoes the read address
in slot 1 followed by the read data in slot 2.
The new function of the ICH6 hardware is to notice which ACZ_SDIN line contains the read return
data, and to set new bits in the new register indicating which ACZ_SDIN line the register read data
returned on. If it returned on ACZ_SDIN[0], bits [1:0] contain the value 00. If it returned on
ACZ_SDIN[1], the bits contain the value 01, etc.
ICH6 hardware can set these bits every time register read data is returned from a function 5 read.
No special command is necessary to cause the bits to be set. The new driver/BIOS software reads
the bits from this register when it cares to, and can ignore it otherwise. When software is
attempting to establish the codec-to-ACZ_SDIN mapping, it will single feed the read request and
not pipeline to ensure it gets the right mapping, we cannot ensure the serialization of the access.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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