82801FB Datasheet, PDF (715/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

High Precision Event Timer Registers
20 High Precision Event Timer
Registers
The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to
directly access each register without having to use an index register. The timer register space is
1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation
with IA64 processors. There are four possible memory address ranges beginning at 1)
FED0_0000h, 2) FED0_1000h, 3) FED0_2000h., 4) FED0_4000h. The choice of address range
will be selected by configuration bits in the High Precision Timer Configuration Register (Chipset
Configuration Registers:Offset 3404h).
Behavioral Rules:
1. Software must not attempt to read or write across register boundaries. For example, a 32-bit
access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h,
03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh. Any accesses to these offsets will result
in an unexpected behavior, and may result in a master abort. However, these accesses should
not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit
boundaries.
2. Software should not write to read-only registers.
3. Software should not expect any particular or consistent value when reading reserved registers
or bits.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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