82801FB Datasheet, PDF (461/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.9
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset: 0Dh
Default Value: 00h
Attribute: RO
Size:
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO. The SATA controller is implemented internally, and is
7:0 ^{not arbitrated as a PCI device, so it does not need a Master Latency Timer.}
00h = Hardwired.
12.1.10
.
PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset: 10h–13h
Default Value: 00000001h
Attribute: R/W, RO
Size:
32 bits
Bit
Description
31:16
15:3
2:1
0
Reserved
Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
12.1.11
.
PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset: 14h–17h
Default Value: 00000001h
Attribute: R/W, RO
Size:
32 bits
Bit
Description
31:16
15:2
1
0
Reserved
Base Address — R/W. This field provides the base address of the I/O space (4 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
461