82801FB Datasheet, PDF (635/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.1.19
HDCTL—Intel^® High Definition Audio Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
Bit
Description
7:4 Reserved.
BITCLK Detect Clear (CLKDETCLR) — R/W.
0 = When a 0 is written to this bit, the clock detect circuit is operational and maybe enabled.
3 ^{1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains clear when}
this bit is set to 1.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
BITCLK Detect Enable (CLKDETEN) — R/W.
2
0 = Latches the current state of bit 1 (CLKDET#) in this register
1 = Enables the clock detection circuit
NOTE: This bit is not affected by the D3_HOT to D0 transition.
BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.
It is set to 0 when the Intel^® ICH6 detects that the BITCLK is toggling, indicating the presence of an
AC ’97 codec on the link.
1
NOTES:
1. Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of this bit and
must be manipulated correctly in order to get a valid CLKDET# indicator.
2. This bit is not affected by the D3_HOT to D0 transition.
Intel High Definition Audio/AC ‘97 Signal Mode — R/W. This bit selects the shared Intel High
Definition Audio/AC ‘97 signals.
0 = AC ’97 mode is selected (Default)
1 = Intel High Definition Audio mode is selected
0
NOTES:
1. This bit has no affect on the visibility of the Intel High Definition Audio and AC ’97 function
configuration space.
2. This bit is in the resume well and only clear on a power-on reset. Software must not makes
assumptions about the reset state of this bit and must set it appropriately.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
635