82801FB Datasheet, PDF (338/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.22
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44–47h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31
30
29: 8
7: 6
5
4
3
2
1
0
Discard Delayed Transactions (DDT) — R/W.
0 = Logged delayed transactions are kept.
1 = The ICH6 PCI bridge will discard any delayed transactions it has logged. This includes
transactions in the pending queue, and any transactions in the active queue, whether in the
hard or soft DT state. The prefetchers will be disabled and return to an idle state.
NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will continue until
either the PCI master disconnects (by de-asserting FRAME#) or the PCI bridge disconnects
(by asserting STOP#). This bit is cleared by the PCI bridge when the delayed transaction
queues are empty and have returned to an idle state. Software sets this bit and polls for its
completion
Block Delayed Transactions (BDT) — R/W.
0 = Delayed transactions accepted
1 = The ICH6 PCI bridge will not accept incoming transactions which will result in delayed
transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory
writes) will still be accepted.
Reserved
Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of delayed
transactions that the ICH6 PCI bridge will run. Encodings are:
00 =) 2 Active, 5 pending
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
Reserved
Auto Flush After Disconnect Enable (AFADE) — R/W.
0 = The PCI bridge will retain any fetched data until required to discard by producer/consumer
rules.
1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-asserting
FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer.
Never Prefetch (NP) — R/W.
0 = Prefetch enabled
1 = The ICH6 will only fetch a single DW and will not enable prefetching, regardless of the
command being an Memory read (MR), Memory read line (MRL), or Memory read multiple
(MRM).
Memory Read Multiple Prefetch Disable (MRMPD) — R/W.
0 = MRM commands will fetch multiple cache lines as defined by the prefetch algorithm.
1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte aligned cache
line.
Memory Read Line Prefetch Disable (MRLPD) — R/W.
0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.
1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line.
Memory Read Prefetch Disable (MRPD) — R/W.
0 = MR commands will fetch up to a 64-byte aligned cache line.
1 = Memory read (MR) commands will fetch only a single DW.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet